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1 ? fn9005.8 isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, ISL6130 power sequencing controllers the intersil isl6123, isl6124, isl6125, isl6126, isl6127, isl6128 and ISL6130 are integrated four channel controlled-on/controlled-off power-supply sequencers with supply monitoring, fault protection and a ?sequence completed? signal (reset#). for larger systems, more than four supplies can be sequenced by simply connecting a wire between sysreset# pins of cascaded ic's. the isl6125 uses four open-drain outputs to control the on/off sequencing of four supplies, while the other sequencers use a patented, micropower 7x charge pump to drive four external low-cost nfet switch gates above the s upply rail by 5.3v. these ic's can be biased from any supply 5v down to 1.5v. individual product descriptions follow. the four channel isl6123 (enable input), isl6124 (enable# input) and isl6125 ics offer the designer 4 rail control when it is required that all four rails are in minimal compliance prior to turn on and that compliance must be maintained during operation. the isl6123 and ISL6130 have a low power standby mode when disabled, suitable for battery powered applications. the isl6125 operates like the isl6124 but instead of charge pump driven gate drive outputs it has open drain logic outputs for direct interface to other circuitry. in contrast to the majority, for both the isl6126 and ISL6130 each of the four channels opera tes independently so that the various gates will turn on once its individually associated input voltage requirements are met. the isl6127 is a pre programmed a-b-c-d turn-on and d-c-b-a turn-off sequenced ic. once all inputs are in compliance and enable is asserted the sequencing starts and each subsequent gate will turn-on after the previous one completes turning-on. the isl6128 has two groups of two channels each with its independent i/o and is ideal for voltage sequencing into redundant capability loads as all four inputs need to be satisfied prior to turn on but a single group fault is ignored by the other group. external resistors provide flexible voltage threshold programming of monitored rail voltages. delay and sequencing are provided by external capacitors for both ramp up and ramp down. additional i/o is provided i ndicating and driv ing reset state in various configurations. for volume applications, other programmable options and features can be had. contact the factory with your needs. features ? enables arbitrary turn-on and turn-off sequencing of up to four power supplies (0.7v to 5v) ? operates from 1.5v to 5v supply voltage ? supplies v dd +5.3v of charge pumped gate drive ? adjustable voltage slew rate for each rail ? multiple sequencers can be daisy-chained to sequence an infinite number of independent supplies ? glitch immunity ? under voltage lockout for each supply ? 1a sleep state ( isl6123, ISL6130 ) ? active high ( isl6123, ISL6130 ) or low ( isl6124, isl6125, isl6126, isl6127, isl6128 ) enable# input ? open drain version available ( isl6125 ) ? voltage determined sequence (i sl6126, ISL6130 ) ? pre-programmed sequence available ( isl6127 ) ? dual channel groupings ( isl6128 ) ? qfn package with pb-free plus anneal option (rohs compliant) applications ? graphics cards ? fpga/asic/microprocessor/powerpc supply sequencing ? network routers ? telecommunications systems pinout isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, ISL6130 (24 ld qfn) top view 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 7 8 9 10 11 12 4mmx4mm enable/ enable# gate_a dly_off_c dly_off_d gate_b gate_c gate_d dly_on_b nc gnd nc uvlo_b dly_off_b uvlo_d dly_on_d dly_on_c uvlo_c dly_off_a nc uvlo_a dly_on_a sysrst# vdd reset# data sheet february 5, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2001, 2003-2007. all rights reserved. all other trademarks mentioned are the property of their respective owners.
2 fn9005.8 february 5, 2007 ordering information part number* part marking temp. range (c) package pkg. dwg. # isl6123ir isl6123ir -40 to +85 24 ld 4x4 qfn l24.4x4 isl6124ir isl6124ir -40 to +85 24 ld 4x4 qfn l24.4x4 isl6125ir isl6125ir -40 to +85 24 ld 4x4 qfn l24.4x4 isl6126ir isl6126ir -40 to +85 24 ld 4x4 qfn l24.4x4 isl6127ir isl6127ir -40 to +85 24 ld 4x4 qfn l24.4x4 isl6128ir isl6128ir -40 to +85 24 ld 4x4 qfn l24.4x4 isl6123irza (note) 6123irz -40 to +85 24 ld 4x4 qfn (pb-free) l24.4x4 isl6124irza (note) 6124irz -40 to +85 24 ld 4x4 qfn (pb-free) l24.4x4 isl6125irza (note) 6125irz -40 to +85 24 ld 4x4 qfn (pb-free) l24.4x4 isl6126irza (note) 6126irz -40 to +85 24 ld 4x4 qfn (pb-free) l24.4x4 isl6127irza (note) 6127irz -40 to +85 24 ld 4x4 qfn (pb-free) l24.4x4 isl6128irza (note) 6128irz -40 to +85 24 ld 4x4 qfn (pb-free) l24.4x4 ISL6130irza (note) 6130irz -40 to +85 24 ld 4x4 qfn (pb-free) l24.4x4 isl612xseqeval1 isl612x evaluation platform isl6125eval1 isl6125 evaluation platform *add ?-t? suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. figure 1. typical isl6123 application usage isl6123 block diagram (1/4) aout ain bin cin din bout cout dout uvlo_b uvlo_a uvlo_d uvlo_c ain dly_on_a dly_off_a dly_off_b dly_off_c dly_off_d dly_on_b dly_on_c dly_on_d enable sysrst# ground bin cin din reset# v dd gate d gate c gate b gate a en sysrst uvlox 0.633v reset# dly_onx 1.26v dly_offx 1.26v gatex logic 1a bias lock out vdd rising delay vdd+5v q-pump 1a 1a -1a 30s filter 150ms rising delay 10ms isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
3 fn9005.8 february 5, 2007 pin descriptions pin # pin name function description 23 vdd chip bias bias ic from nominal 1.5v to 5v 10 gnd bias return ic ground 1 enable_1/ enable#_1 input to start on/off sequencing. input to initiate the start of the programmed sequencing of supplies on or off. enable functionality is disabled for 10ms after uvlo is satisfied. isl6123 and ISL6130 have enable. isl6124, isl6125, isl6126 and isl6127 have enable#. only isl6128 has 2 enable# inputs, 1 for each 2 channel grouping. en_1# for (a, b), and en_2# for (c, d). 11 enable#_2 24 reset# reset# output reset# provides a low signal 150ms after all gates are fully enhanced. this delay is for stabilization of output voltages. reset# will assert low upon uvlo not being satisfied or enable/enable# being deasserted. the reset outputs are open drain n channel fet and is guaranteed to be in the correct state for vdd down to 1v and is filtered to ignore fast transients on vdd and uvlo_x. reset#_2 only exists on isl6128 for (c, d) group i/o. 9 reset#_2 20 uvlo_a under voltage lock out/monitoring input these inputs provide for a programmable uv lockout referenced to an internal 0.633v reference and are filtered to ignore short (<30s) transients below programmed uvlo level. 12 uvlo_b 17 uvlo_c 14 uvlo_d 21 dly_on_a gate on delay timer output allows for programming the delay and sequence for vout turn-on using a capacitor to ground. each cap is charged with 1a, 10ms after turn-on initiated by enable/enable# with an internal current source providing delay to the associated fets gate turn-on. these pins are nc on isl6126, isl6127 and ISL6130. 8dly_on_b 16 dly_on_c 15 dly_on_d 18 dly_off_a gate off delay timer output allows for programming the delay and sequence for vout turn-off through enable/enable# via a capacitor to ground. each cap is charged with a 1a internal current source to an internal reference voltage causing the corresponding gate to be pulled down turning-off the fet. these pins are nc on isl6127. 13 dly_off_b 3 dly_off_c 4 dly_off_d 2 gate_a fet gate drive output isl6125 open drain outputs drives the external fets with a 1a current source to soft start ramp into the load. on the isl6125 only, these are open drain outputs that can be pulled up to a maximum of vdd voltage. 5gate_b 6gate_c 7gate_d 22 sysrst# system reset i/o as an input, allows for immediate and unconditional latch-off of all gate outputs when driven low. this input can also be used to initiate the programmed sequence with ?zero? wait (no 10ms stabilization delay) from input signal on this pin being driven high to first gate. as an output when there is a uv condition, this pi n pulls low. if common to other sysrst# pins in a multiple ic configuration, it will cause immediate and unconditional latch-off of all other gates on all other isl612x sequencers. this pin is a nc on isl6126 and isl6128 and ISL6130. 19 no connect no connect no connect isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
4 fn9005.8 february 5, 2007 isl612x variant feature matrix part name en/en# cmos/ ttl gate drive or open drain outputs required conditions for initial start-up number of uvlo inputs monitored by each reset# number of channels that turn-off when 1 uvlo faults preset or adjustable sequence number of uvlo and pairs of i/o features isl6123 en ttl gate drive 4 uvlo 1 en 4 uvlo 4 gates time adjustable on and off 4 monitors with 1 i/o auto restart, low bias current sleep isl6124 en# cmos gate drive 4 uvlo 1 en 4 uvlo 4 gates time adjustable on and off 4 monitors with 1 i/o auto restart isl6125 en# cmo open drain 4 uvlo 1 en 4 uvlo 4 open drain time adjustable on and off 4 monitors with 1 i/o auto restart, open drain sequenced outputs isl6126 en# cmos gate drive 1 uvlo 1 en 4 uvlo 1 gate voltage determined on time adjustable off 4 monitors with 1 i/o gates independent on as uvlo valid isl6127 en# cmos gate drive 4 uvlo 1 en 4 uvlo 4 gates preset 4 monitors with 1 i/o auto restart isl6128 en# cmos gate drive 4 uvlo 2 en 2 uvlo 2 gates preset 2 monitors with 2 i/o dual redundant operation ISL6130 en ttl gate drive 1 uvlo 1 en 4 uvlo 1 gates voltage determined on time adjustable off 4 monitors with 1 i/o gates independent on as uvlo valid low bias current sleep isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
5 fn9005.8 february 5, 2007 absolute maximum rati ngs thermal information v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0v gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +6v isl6125 logic out. . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v uvlo, enable, enable#, sysrst# . . . . . . -0.3v to v dd +0.3v reset#, dly_on, dlyoff . . . . . . . . . . . . . . . -0.3v to v dd +0.3v operating conditions v dd supply voltage range . . . . . . . . . . . . . . . . . . . . +1.5v to +5.5v temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical, notes 1, 2) ja (c/w) jc (c/w) 4 x 4 qfn package . . . . . . . . . . . . . . . 48 9 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . +125c maximum storage temperature range . . . . . . . . . .-65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . +300c (qfn - leads only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 3. all voltages are relative to gnd, unless otherwise specified. electrical specifications v dd = 1.5v to +5v, t a = t j = -40c to +85c, unless otherwise specified. parameter symbol test conditions min typ max unit uvlo falling undervoltage lockout threshold v uvlovth t j = +25c 619 633 647 mv undervoltage lockout threshold tempco tc uvlovth t j = -40c to +85c 40 nv/c undervoltage lockout hysteresis v uvlohys 10 mv undervoltage lockout threshold range ruvlovth max v uvlovth - min v uvlovth 7mv undervoltage lockout delay tuvlodel enable satisfied 10 ms transient filter duration tfil v dd , uvlo, enable glitch filter 30 s delay on/off delay charging current dly_ichg v dly = 0v 0.92 1 1.08 a delay charging current range dly_ichg_r dly_ichg(max) - dly_ichg(min) 0.08 a delay charging current temp. coeff. tc_dly_ichg 0.2 na/c delay threshold voltage dly_vth 1.238 1.266 1.294 v delay threshold voltage temp. coeff. tc_dly_vth 0.2 mv/c enable/enable#, reset# & sysrst# i/o enable threshold v enh 1.2 v enable# threshold v enh 0.5 v dd v enable/enable# hysteresis v enh - v enl measured at v dd = 1.5v 0.2 v enable/enable# lockout delay tdelen_lo uvlo satisfied 10 ms enable/enable# input capacitance cin_en 5 pf reset# pull-up voltage vpu_rst v dd v reset# pull-down current i rst pd1 v dd = 1.5v, rst = 0.1v 5 ma i rst pd3 v dd = 3.3v, rst = 0.1v 13 ma i rst pd5 v dd = 5v, rst = 0.1v 17 ma reset# delay after gate high t rst del gate = v dd +5v 160 ms reset# output low v rst l measured at v dd = 5v with 5k pull-up resistors 0.1 v reset output capacitance cout_rst 10 pf isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
6 fn9005.8 february 5, 2007 descriptions and operation the isl612x sequencer family consists of several four channel voltage sequencing controllers in various functional and personality configurations. all are designed for use in multiple-voltage systems requiring power sequencing of various supply voltages. individual voltage rails are gated on and off by external n-channel mosfets, the gates of which are driven by an internal charge pump to v dd +5.3v (vqp) in a user programmed sequence. with the four-channel isl6123 the enable must be asserted high and all four voltages to be sequenced must be above their respective us er programmed under voltage lock out (uvlo) levels before programmed output turn on sequencing can begin. sequencing and delay determination is accomplished by the choice of external cap values on the dly_on and dly_off pins. once all four uvlo inputs and enable are satisfied for 10ms, the four dly_on caps are simultaneously charged with 1a current sources to the dly_vth level of 1.27v. as each dly_on pin reaches the dly_vth level its associated gate will then turn-on with a 1a source current to the vqp voltage of v dd +5.3v. thus all four gates will sequentially turn on. once at dly_vth the dly_on pins will discharge to be ready when next needed. after the entire turn on sequence has been completed and all gates have reached the charge pumped voltage (vqp), a 160ms delay is started to ensure stability after which the reset# output will be released to go high. subsequent to turn-on, if any input falls below its uvlo point for longer than the glitch filter period (~30 s) this is considered a fault. reset# and sysrst# are pulled low and all gates are simultaneously also pulled low. in this mode the gates are pulled low with 88ma. normal shutdown mode is entered when no uvlo is violated and the enable is deasserted. when enable is deasserted, reset# is asserted and pulled low. next, all four shutdown ramp caps on the dly_off pins are charged with a 1 a source and when any ramp-cap reaches dly_vth, a latch is set and a current is sunk on the respecti ve gate pin to turn off its external mosfet. when the gate voltage is approximately 0.6v, the gate is pulled down the rest of the way at a higher current level. each individual external fet is thus turned off removing the voltages from the load in the programmed sequence. sysrst# pull-up voltage vpu_srst v dd v sysrst# pull-down current ipu_1.5 v dd = 1.5v 5 a ipu_5 v dd = 5v 100 a sysrst# low output voltage vol_srst v dd = 1.5v, i out = 100 a150mv sysrst# output capacitance cout_srst 10 pf sysrst# low to gate turn-off t delsys_g gate = 80% of v dd +5v 40 ns gate gate turn-on current i gateon gate = 0v 0.8 1.1 1.4 a gate turn-off current i gateoff_l gate = v dd , disabled -1.4 -1.05 -0.8 a gate current range i gate_range within ic i gate max-min 0.35 a gate turn-on/off current temp. coeff. tc_i gate 0.2 na/c gate pull-down high current i gateoff_h gate = v dd , uvlo = 0v 88 ma gate high voltage v gateh v dd < 2v, t j = +25c v dd +4.9v v v gateh v dd > 2v v dd +5v v dd +5.3v v gate low voltage v gatel gate low voltage, v dd = 1v 0 0.1 v bias ic supply current i vdd_5v v dd = 5v 0.20 0.5 ma i vdd_3.3v v dd = 3.3v 0.14 ma i vdd_1.5v v dd = 1.5v 0.10 ma isl6123, ISL6130 stand by ic supply current i vdd_sb v dd = 5v, enable = 0v 1 a v dd power on reset v dd _por 1 v electrical specifications v dd = 1.5v to +5v, t a = t j = -40c to +85c, unless otherwise specified. (continued) parameter symbol test conditions min typ max unit isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
7 fn9005.8 february 5, 2007 the isl6123 and isl6124 have the same functionality except for the enable ac tive polarity with the isl6124 having an enable# input. additionally the isl6123 and ISL6130 also have an ultra low power sleep state when enable is low. the isl6125 has the same personality as the isl6124 but instead of charged pump driven gate outputs it has open drain outputs that can be pulled up to a maximum of v dd . the isl6126 and ISL6130 are different in that their sequence on is not time determined but voltage determined. its personality is th at each of the four channels operates independently so that once the ic is biased and any one of the uvlo inputs is greater than the 0.63v internal reference, and the enable input is also satisfied the gate for the associated uvlo input will turn-on. in turn, the other uvlo inputs need to be satisfied for the associated gates to turn-on. 150ms after all gates are fully on (gate voltage = vqp), the reset# is released to go high. the uvlo inputs can be driven by either a previously turned on output rail offering a voltage determined sequence or by logic signal inputs. any subsequent uvlo level < its programmed level will pull the associated gate and reset# output low (if previously released), but will not latch-off the other gates. predetermined turn-off is accomplished by deasserting enable, this will cause reset# to latch low and all four gate outputs to follow the programmed turn off sequence similar to a isl6124. the isl6127 is a four-channel seque ncer pre-programmed for a-b-c-d turn-on and d-c-b-a turn-off. after all four uvlo and enable# inputs are satisfied for ~10ms, the sequencing starts and the next gate in the sequence starts to ramp up once the previous gate has reached ~vqp-1v. 160ms after the last gate is at vqp the reset# output will be deasserted. once any uvlo is unsatisfied, reset# is pulled low, sysrst# is pulled low and all gates are simultaneously turned off. when enable# is signaled high the d gate will start to pull low and once below 0.6v the next gate will then start to pull low and so on until all gates are at 0v. unloaded, this turn off sequence will complete in <1ms. this variant offers a lower cost and size implementation as the external delay caps are not used. since the delay caps are not used this ic can not delay the start of subsequent gates thus necessary stabilization or system house keeping need to be considered. the isl6128 is a four-channel device that groups the four channels into two groups of two channels each, as a, b and c, d, each group having its own enable# and reset# i/io pins. this requires all four uvlo and both enable#s to be satisfied for sequencing to start. the a, b group will first turn on 10ms after the second enable# is pulled low with a then b turning on followed by c then d. once the preceding gate = vqp the next dly_on pin starts to charge its capacitor thus turning on all four gates. approximately 160ms after d gate = vqp the reset# output is released to go high. once any uvlo is unsatisfied, only the related group?s reset# and two gates are pulled low. the related en input has to be cycled for the faulted group to be turned-on again. normal shutdown is invoked by either signaling both enable# inputs high which will cause all the two related gates to shutdown in reverse order from turn- on. dly_x caps adjust the delay between gates during turn on and off but not the order. during bias up the reset# output is guaranteed to be in the correct state with v dd lower than 1v. the sysrst# pin follows the v dd upon power up with a weak internal pull-up and is both an input and output connection providing two functions. as an input, if it is pulled low all gates will be unconditionally shut off and reset# pulls low, see figure 6. this input can also be used as a no wait enabling input, if all inputs (enable and uvlo) are satisfied it does not wait through the ~10ms enable delay to initiate dly_on cap charging when released to go high. as an output it is useful when implementing multiple sequencers in a design needing simultaneous shutdown as with a kill switch across all sequencers. on ce any uvlo is unsatisfied longer than t fil the related sysrst# will pull low and pull all other sysrst# inputs low that are on a common connection thus unconditionally shutting down all outputs across multiple sequencers. except for isl6128 after a fault, restart of the turn on sequence is automatic once all requirements are met. this allows for no interaction between the sequencer and a controller ic if desired. the enable & reset# i/o do allow for a higher level of feedback and control if desired. the isl6128 requires that the related enable# be cycled for restart of its associated group gates. if no capacitors are connected between dly_on or dly_off pins and ground then all such related gates start to turn on immediately after the 10ms (t uvlodel ) enable stabilization time out has expired and the gates start to immediately turn off when enable is asserted. if some of the rails are to be sequenced together, in order to eliminate the effect of capacitor variance on the timing and to reduce cost, a common capacitor can be connected to two or more dly_on or dly_off pins. in this case multiply the capacitor value by the number of common dly_x pins to retain the desired timing. table 1 illustrates the nominal time delay from the start of charging to the 1.27v reference for various capacitor values on the dly_x pins. this table does not include the 10ms of enable lock out delay during a start up sequence but represents the time from the end of the enable lock out delay to the start of gate transition. there is no enable lock out delay for a sequence off, so this table illustrates the delay to gate transition from a disable signal. isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
8 fn9005.8 february 5, 2007 figure 2 illustrates the turn-on and figure 3 illustrates the nominal turnoff timing diagram of the isl6123 and isl6124 product. the isl6125 is similar to the isl6124 except that instead of charge pumped gate outputs, there are sequenced open drain outputs that can be pulled up to a maximum of v dd . note the delay and flexible sequ encing possibilities. multiple series, parallel or adjustable capacitors can be used to easily fine tune timing between that offered by standard value capacitors. l table 1. nominal delay to sequencing threshold dly pin capacitance time(s) open 0.00006 100pf 0.00013 1000pf 0.0013 0.01 f 0.013 0.1 f0.13 1 f1.3 10 f13 note: nom. t del_seq = cap ( f) * 1.3m . figure 2. isl6123, isl6124 turn-on a nd glitch response timing diagram uvlo_b uvlo_c uvlo_d enable (isl6123) reset# dlyon_a dlyon_b dlyon_c dlyon_d gate_a gate_b gate_c gate_d uvlo_a v en dly_vth dly_vth dly_vth dly_vth v qpump v qpump v qpump enable# (isl6124) v uvlovth v uvlovth v uvlovth v uvlovth t rstdel t uvlodel v qpump -1v v qpump ISL6130
9 fn9005.8 february 5, 2007 isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130 figure 3. isl6123, isl6124 turn-off timing diagram enable# (isl6124) reset# dlyoff_a dlyoff_b dlyoff_c dlyoff_d gate_d gate_c gate_b gate_a enable (isl6123) v en uvlo_x>vuvlovth dly_vth dly_vth dly_vth dly_vth typical performance curves figure 4. uvlo threshold voltage figure 5. dly charge current 634 633 632 631 628 626 uv threshold (mv) temperature (c) 627 -40 0 20 60 -20 40 80 100 630 629 v dd = 5v v dd = 1.5v dly current source (a) -40 0 20 60 -20 40 80 100 temperature ( c ) 1.03 1.02 0.97 0.98 0.99 1.00 1.01 1.04 dly_off/on v dd = +5v v dd = 1.5v
10 fn9005.8 february 5, 2007 using the isl612xseqeval1 platform the isl612xseqeval1 platform is the primary evaluation board for this family. the board has two comple te, separate and electrically identical circuits. see figure 15 for its schematic and photograph. addi tionally, there is an isl6125 specific eval platform, isl6125eval1 , due to its unique open drain outputs for ease of evaluation. see figure 16 for its schematic and photograph. in the top right hand corner of the board is a smd layout with a isl6123 illustrating the full functionality and small implementation size for an application having the highest component count. the majority of the board is given over to a socket and discrete through-hole components circuit for ease of evaluation flexibility through ic variant swapping and modification of uvlo levels and sequencing order by passive component substitution. the board is shipped with the isl6123 installed in both locations and with two each of the other released variant types loose packed. as this sequencer family has a common function pinout there are no major modifications to the board necessary to evaluate the other ics. to the left, right and above the socket are four test point strips (tp1, tp2, tp3, tp4). these give access to the labeled ic i/o pins during evaluation. remember that significant current or capacitive loading of particular i/o pins will affect functionality and performance. attention to orientation and placement of variant ics in the socket must be paid to prevent ic damage or faulty evaluation. the default configuration of the isl612xseqeval1 circuitries was built around the following design assumptions: 1. using the isl6123ir or isl6124ir 2. the four supplies being s equenced are 5v (in_a), 3.3v (in_b), 2.5v (in_c) and 1.5v (in_d), the uvlo levels are ~80% of nominal voltages. resistors chosen such that the total resistance of each divider is ~10k using standard value resistors to approximate 80% of nominal = 0.63v on uvlo input. resistor choice is such that i x r2 = 0.633v at the desired uv (undervoltage) level as the monitored voltage decreases. total resistance in the divider is a factor for the designer to consider for accuracy of uv level and efficiency vs electrical noise immunity trade-offs. 3. the desired order turn-on sequence is first both 5v and 3.3v supplies together and then the 2.5v supply about 75ms later and lastly the 1.5v supply about 45ms later. 4. the desired turn-off sequence is first both 1.5v and 3.3v supplies at the same time t hen the 2.5v supply about 50ms later and lastly the 5v supply about 72ms after that. all scope shots are taken from isl612xseqeval1 board. figures 7 and 8 illustrate the desired turn-on and turn-off sequences respectively. the sequencing order and delay between voltages sequencing is set by external capacitance values, so other than illu strated can be accomplished. figure 6. sysrst# low to output latch off typical performance curves (continued) 1 s/div 5vout gate sysrst# 2v/div 3.3vout vmonitored r1 r2 uvlo vmon/0.633mv = r1+r2/r2 when vmon = desired uv level as vmon decreases. for example, a 5v supply with a desired uv level at 4v would mean r1+r2/r2 = 6.319. ideally, any r1 and r2 combination that met this ratio would work, but with only standard value resistors av ailable, small deviations will occur. isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
11 fn9005.8 february 5, 2007 figures 9 and 10 illustrate the timing relationships between the en input, reset#, dly and gate outputs and the vout voltage for a single channel being turned on and off respectively. reset# is not show n in figure 9 as it asserts 160ms after the last gate goes high. all ic family variants share simi lar function for dly_x capacitor charging, gate and reset# operation. figures 11 through 14 illustrate the principal feature and functional differences for each of the isl6125, isl6126, isl6127 and isl6128 variants. figure 11 features the isl 6125 open drain outputs being sequenced on and off along with reset# rela tionship which is similar to all other family variants. figure 12 illustrates the indep endent input feature of the isl6126 which allows once the en# is low for each uvlo to be individually satisfied and for its associated gate to turn-on. only when the last variable vin is satisfied as shown does the reset# release to signal all input voltages are valid. figure 13 shows the isl6127 pre-programmed abcd on dcba off order of sequencing with minimal non-adjustable delay between each. figure 14 demonstrates the independence of the redundant two rail sequencer. it shows that either one of the two groups can be turned off and the abcd order of restart with capacitor programmable delay once both en inputs are pulled low. using the isl6125eval1 platform the isl6125eval1 is the isl6125 specific evaluation board providing for easy evaluation of the isl6125 with its unique open drain outputs. the uvlo levels, sequence and delays are programmed exactly like t he other isl612x ics but the isl6125 has sequenced open drain outputs rather than charge pumped driven gate outputs. see figure 16 for its schematic and photograph. typical performance waveforms figure 7. isl6124 sequenced turn-on figure 8. isl6124 sequenced turn-off figure 9. isl6123 single channel turn-on figure 10. isl6123 single channel turn-off 1v/div 40ms/div 5vout 3.3vout 2.5vout reset# enable# 1.5vout 1v/div 20ms/div 5vout 3.3voutput 2.5vout 1.5vout enable# 10ms/div gate 2v/div dly_vth en 2v/div dly_on 1v/div 3.3vo 1v/div t delenlo 4ms/div 3.3vo 1v/div reset# 2v/div gate 2v/div en 2v/div dly_off 1v/div dly_vth isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
12 fn9005.8 february 5, 2007 figure 11. isl6125 logic outputs sequenced on and off and reset# relationship figure 12. isl6126 uvlo input/output independence and reset# relationship figure 13. isl6127 preprogrammed abcd turn-on and dcba turn-off figure 14. isl6128 group i ndependent t urn-off and delay adjustable pre programmed turn-on typical performance waveforms (continued) en# reset# logic a -d 100ms/div sequenced outputs vin_var static en/all other vout reset# 100ms/div trstdel vout_var a_vout b_vout c_vout d_vout en#_1 5v/div b_vout c_vout d_vout a_vout en#_2 5v/div isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
13 fn9005.8 february 5, 2007 inc = +2.5v ind = +1.5v inb = +3.3v ina and vdd = +5v c1 1 f c2 0.01 f 0.1 f 0.01 f 0.068 f c6 c7 c3 c4 0.047 f c5 0.01 f c8 0.01 f c9 0.1 f nc sysrst# gnd reset#1 reset#2 gate_d gate_c gate_b gate_a isl612xir uvlo_a dly_off_b uvlo_c uvlo_d uvlo_b dly_off_d dly_off_c dly_on_a s1 dly_on_c dly_on_d dly_on_b v dd enable2 enable1 3.01k 1.47k 4.99k r2 r6 en1 en2 r1 r3 r5 r7 7.681k 4.99k 8.45k 12 14 17 20 22 19 r9 750 r10 20 1 750 2 5 6 7 sysrst# 3 4 13 18 21 16 15 8 23 q3 4 5 3 2 q3 7 5 6 rl8 10 rl7 5 rl6 5 rl5 2 2 4 3 si4922dy si4922dy si4922dy 8 6 si4922dy 1 8 q4 dly_off_a r4 r8 10 1 11 9 24 2.26k figure 15. eval board channel 1 sche matic and isl612xseqeval1 photograph 7 1 q4 6.98k isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
14 fn9005.8 february 5, 2007 figure 16. isl6125eval1 schematic and photograph 4.99k r6 1.5v_(inc) 2.5v_(ind) 7.68k r2 6.98k r4 4.99k 1.47k 14 u1 21 1f 20 r12 isl612x 17 11 10 r5 seq_d seq_a r10 r8 c8 c9 c6 c4 c7 c3 c2 d1 r7 r3 r11 c1 open 0.1f 0.01f open 0.01f 0.047f 2.26k 3.01k 10k 10k 10k 750 0.022f 0.068f c5 r1 8 15 16 3 4 13 18 2 5 6 24 25 9 12 1 23 r9 10k seq_b seq_c 19 r13 7 22 gate_c gate_b gate_a dly_off_a dly_off_b dly_off_d dly_off_c dly_on_d dly_on_b vdd uvlo_b uvlo_d uvlo_c uvlo_a ep gnd dly_on_c dly_on_a gate_d nc nc sysrst enable reset a a 3.3v_(inb) 5.0v_(ina) 8.45k 21 reset agnd sysrst enable r2 isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
15 fn9005.8 february 5, 2007 table 2. isl612xseqeval1 board channel 1 component listing component designator component function component description s1 isl612x , 4 supply sequencer socket intersil, isl612x 4 supply sequencer socket q3, q4 voltage rail switches si4922dy or equivalent, dual 8a, 30v, 0.018 , n-channel mosfet r7 5v to uvlo_a resistor for divider string 8.45k 1%, 0402 r8 uvlo_a to gnd resistor for divider string 1.47k 1%, 0402 r1 3.3v to uvlo_b resistor for divider string 7.68k 1%, 0402 r2 uvlo_b to gnd resistor for divider string 2.26k 1%, 0402 r5 2.5v to uvlo_c resistor for divider string 6.98k 1%, 0402 r6 uvlo_c to gnd resistor for divider string 3.01k 1%, 0402 r3 1.5v to uvlo_d resistor for divider string 4.99k 1%, 0402 r4 uvlo_d to gnd resistor for divider string 4.99k 1%, 0402 r9 reset#1 led current limiting resistor 750 10%, 0805 r10 reset#2 led current limiting resistor 750 10%, 0805 c7 5v turn-on delay cap. (13ms) 0.01f 10%, 6.3v, 0402 c9 5v turn-off delay cap. (130ms) 0.1f 10%, 6.3v, 0402 c2 3.3v turn-on delay cap. (13ms) 0.01f 10%, 6.3v, 0402 c5 3.3v turn-off delay cap. (3ms) 0.01f 10%, 6.3v, 0402 c3 2.5v turn-on delay cap. (88ms) 0.068f 10%, 6.3v, 0402 c4 2.5v turn-off delay cap. (61ms) 0.047f 10%, 6.3v, 0402 c6 1.5v turn-on delay cap. (130ms) 0.1f 10%, 6.3v, 0402 c8 1.5v turn-off delay cap. (13ms) 0.01f 10%, 6.3v, 0402 c1 decoupling capacitor 0.1f, 0805 d1 reset#1 indicating led 0805, smd leds red d2 reset#2 indicating led 0805, smd leds red rl8 5v load resistor 10 20%, 3w carbon rl7 3.3v load resistor 5 20%, 3w carbon rl6 2.5v load resistor 5 20%, 3w carbon rl5 1.5v load resistor 2 20%, 3w carbon isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
16 fn9005.8 february 5, 2007 application implementations multiple sequencer implementations in order to control the sequencing of more than 4 voltages, several of the isl6123, isl6124, isl6125 or isl6127 devices can be variously configured together to accomplish this. there may be concerns of a particular implementation that would make a particular configuration preferable over another. the fundamental questions to answer to determine which configuration is best suited for your applications are: 1. what level of voltage assurance is needed prior to sequencing on and can the voltage supplies be grouped into high and low criticality? 2. is there a critical maximum time window all supplies must be present at load or is there a first and a second group preference possibly with some work done in between the two groups of voltages being present? three configurations are described and illustrated here. in applications where the integrit y of critical voltages must be assured prior to sequencing, additional monitoring of the critical supplies is needed. if t he compliance of the voltage is critical for either undervolt age and/or overvoltage, the isl613x family of supervisors can be employed to provide this additional assurance across multiple sequencers. see document fn9115 for supervisor data sheet. figure 17 is a block diagram of this voltage compliant, high assurance, low risk configuration showing the isl613x supervisor and a mix of fet switched outputs a nd logic output sequencers (isl6124 and isl6125 ics). table 3. isl6125eval1 component listing component designator component function component description u1 isl6125 , four supply sequencer intersil, isl6125, four supply sequencer with open drain outputs r6 5v to uvlo_a resistor for divider string 8.45k 1%, 0402 r12 uvlo_a to gnd resistor for divider string 1.47k 1%, 0402 r1 3.3v to uvlo_b resistor for divider string 7.68k 1%, 0402 r11 uvlo_b to gnd resistor for divider string 2.26k 1%, 0402 r2 2.5v to uvlo_d resistor for divider string 6.98k 1%, 0402 r3 uvlo_d to gnd resistor for divider string 3.01k 1%, 0402 r4 1.5v to uvlo_c resistor for divider string 4.99k 1%, 0402 r5 uvlo_d to gnd resistor for divider string 4.99k 1%, 0402 r9 reset led current limiting resistor 750 10%, 0805 c5 5v turn-on delay cap. a dnp, 0402 c9 5v turn-off delay cap. a (135ms) 0.1f 10%, 6.3v, 0402 c2 3.3v turn-on delay cap.b (13.7ms) 0.01f 10%, 6.3v, 0402 c8 3.3v turn-off delay cap. b (13.7ms) 0.01f 10%, 6.3v, 0402 c3 2.5v turn-on delay cap.d (28ms) 0.022f 10%, 6.3v, 0402 c7 2.5v turn-off delay cap. d dnp, 0402 c4 1.5v turn-on delay cap. c (98ms) 0.068f 10%, 6.3v, 0402 c6 1.5v turn-off delay cap. c (59ms) 0.047f 10%, 6.3v, 0402 c1 decoupling capacitor 0.1f, 0805 d1 reset#1 indicating led 0805, smd led r8 seq_output_a pull-up resistor 10k , 0402 r9 seq_output_b pull-up resistor 10k , 0402 r10 seq_output_c pull-up resistor 10k , 0402 r13 seq_output_d pull-up resistor 10k , 0402 isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
17 fn9005.8 february 5, 2007 if the mere presence of some voltage potential is adequate prior to sequencing on, then a small number of standard logic and gates can be used to accomplish this. the block diagram in figure 18 illustrates this voltage presence configuration. in either case, the sequencing is straight forward across multiple sequencers as all dly_on capacitors will simultaneously start charging ~10ms after the common enable input signal is delivered. this allows the choice of capacitors to be related to each other no different than using a single sequencer. when the common enabling signal is deasserted these configurati ons will then execute the turn-off sequence across all sequencers as programmed by the dly_off capacitor values. in both cases, with all the sysrst# pins bussed together, once the on sequence is complete, simultaneous shutdown upon any uvlo input failure is assured as sysrst# output will momentarily pull low turning off all gate and logic outputs. there may be applications that require or allow groups of supplies being brought up in sequence and supplies within each group to be sequenced. figure 19 illustrates such a configuration that allows the fi rst group of supplies to turn-on before the second group starts. this arrangement does not necessarily preclude adding the assurance of all supplies prior to turn-on sequencing as previously shown but it will prevent the turn-on sequence from completing if there is one unsatisfied uvlo input in a gr oup. using this configuration involves waiting through the t uvlodel and t rst del (total of ~160ms) for each sequencer ic in the chain for the final reset# to release. once enabl e on the first sequencer is deasserted all the reset# outputs will qui ckly pull low and thus allow the sequenced turn-off of this configuration to ripple through several banks as quickly as the user programmed sequence as chosen by the dly_off capacitors allow. once again with common bussed sysrts# pins, simultaneous shut down of all gates and logic down upon an unsatisfied uvlo input is assured once all fets or logic output are on. if a gate drive option ic is used to drive both fets and logic signals then care to ensure the charged pump gate does not over drive and damage the logic input must be taken. a simple resistor divider can be used to lower the gate voltage to a suitable voltage for the logic input as shown in figure 19. figure 17. isl612x and isl613x voltage compliant sequencing block diagram isl6125 enable# # n+1 isl6124 enable# # n isl613xs monitoring on all rails uvlo uvlo vmon pgood g a t e l power supply sysrst# sysrst# en reset# reset# reset# o g i c oe low = reset figure 18. multiple isl612x using logic gates for voltage presence detect isl6125 enable# # n+1 isl6124 enable# # n uvlo uvlo g a t e l power supply sysrst# sysrst# en reset#? reset# reset# o g i c uvlo oe low = reset isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
18 fn9005.8 february 5, 2007 voltage tracking in some applications the variou s voltages may have to track each other as they ramp up and down, whereas others may just need sequencing. in these cases tracking can be accomplished and has been demonstrated over a wide range of load current (1a to 10a) and load capacitance (10f to 3300f) with the isl612x family. figure 20 and figure 21 illustrate output voltage ramping tracking performance, note that differenc es are less than 0.5v. with the relevant gate pins tied togeth er in a star pattern, so that the resistance between any two gate pins is equivalent (1k to 10k) results in a sharing of the gate ramping voltage and with the same or similar enough fets this behavior is observed. it is suggested that this circ uit implementation be prototyped and evaluated for the particular expected loads prior to committing to manufacturing build. figure 19. multiple isl612x serial configuration isl6125 enable# # n+1 isl6124 enable# # n uvlo uvlo g a t e l power supply sysrst# sysrst# reset# reset# reset# o g i c oe low = reset enable reset# to logic input figure 20. output voltage on low to high tracking figure 21. output voltage high to low tracking isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
19 fn9005.8 february 5, 2007 negative voltage sequencing the isl612x family can use the charged pump gate output to drive fets that would control and sequence negative voltages down to a nominal -5v with minimal additional external circuitry. figure 22 shows turn-on of 5v bipolar supplies together, then the +2.5v and turn-off of both positive supplies being turned off together after the -5v. figure 23 shows the minimal additional external circuitry to accomplish this. the 5v zener diode is used to level shift the gate drive down 5v to prevent premature turn-on when gate = 0v. once gate drive voltage > vz, then fet vgs > 5v, ensuring full turn-on once gate gets to vdd+5.3v. turn-on and turn-off ramp rate can be adjusted with fet gate series resistor value. sequencing of the -v rail is accomplished as normal via the dly_x capacitor value although adjustments in prototyping should be factored in to fine tune for actual circuit requirements. figures 24 and 25 illustrate a high accuracy -v detection circuit using the isl6131 and a low cost low accuracy -v detect circuit and respectively. application considerations timing error sources in any system there are variance contributors, for the isl612x family the timing errors are main ly contributed by three sources. capacitor timing mismatch error obviously, the absolute capacitor value is an error source, thus lower percentage tolerance capacitors help to reduce this error source. figure 26 illu strates a difference of 0.57ms between two dly_x outputs ramping to dly_x threshold voltage, these 5% capacitors were from a common source. in applications where two or more gates or logic outputs must have concurrent transitions, it is recommended that a common gate drive be used to eliminate this timing error. figure 22. voltage sequencing figure 23. -voltage fet drive circuit isl612x gate -vin -vout d1 r1 additional 2 components necessary for -v control and sequencing. d1 necessary to prevent premature turn-on. r1 is used to hold fet vgs = 0v until d1 vz is overcome. r1 value can be changed to adjust -v ramp rates. choose a r1 value between 4m and 10m initially and fine tune resistor value for the particular need. figure 24. hgh accuracy -v lock out figure 26. capacitor timing mismatch isl6131 or isl6536a -v +v to uvlo of isl612x for -v control and sequencing r1 r2 r3 r4 r5 r6 r1 and r2 define -v uvlo level r3 ensures supervisor (isl613 1 or isl6536a) pgood pull-up r4 and r5 provide q1 gate bias between 0v and +v q1 si1300dl -bias vmon pgood +bias (1k) (10k) (15k) to 0v (resistor values suitable for -v = -5v and +v = +3.3v) or equiv. +v -v to uvlo of isl612x for control and sequencing of -v r1 r2 chose r1 and r2 values to drive uvlo high when -v is sufficiently present figure 25. low accuracy -v presence detection isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9005.8 february 5, 2007 dly_x threshold voltage and charging current mismatch the two other error sources come from the ic itself and are the differences in the dly_x threshold voltage, (dly_vth) when the gate charging latch is set and the dly_x charging current, (dly_ichg) across the four individual i/os. both of these parameters are bounded by specification and figure 27 illustrates that with a common capacito r the typical error contributed by these fact ors is insignificant as both dly_x traces overlay each other. figure 27. dly_vth and dly_ichg timing mismatch isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130
21 fn9005.8 february 5, 2007 isl6123, isl6124, isl6 125, isl6126, isl6127 , isl6128, ISL6130 package outline drawing l24.4x4 24 lead quad flat no-lead plastic package rev 4, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 10 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 10 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

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